The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7709879 B1

PDF
Full Text
Expired
Date of Patent:
May. 04, 2010

Filed:

Jun. 03, 2005
Applicants:

Robertus Theodorus Fransiscus Van Schaijk, Leuven, BE;

Michiel Jos Van Duuren, Leuven, BE;

Assignee:

NXP B.V., Eindhoven, NL;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention provides a non-volatile memory device and a method for manufacturing such a device. The device comprises a floating gate (), a control gate () and a separate erase gate (). The erase gate () is provided in or on isolation zones () provided in the substrate (). Because of that, the erase gates () do not add to the cell size. The capacitance between the erase gate () and the floating gate () is small compared with the capacitance between the control gate () and the floating gate (), and the charged floating gate () is erased by Fowler-Nordheim tunneling through the oxide layer between the erase gate () and the floating gate ().


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Van Schaijk, Robertus Theodorus Fransiscus. (2010). Non-volatile memory with erase gate on isolation zones (U.S. Patent No. 7709879). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7709879

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