The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2010

Filed:

Sep. 04, 2007
Applicants:

Timothy G. Dunham, South Burlington, VT (US);

Robert K. Leidy, Burlington, VT (US);

Kevin N. Ogg, Burlington, VT (US);

Richard J. Rassel, Colchester, VT (US);

Valarmathi C. Shanmugam, Essex Junction, VT (US);

Inventors:

Timothy G. Dunham, South Burlington, VT (US);

Robert K. Leidy, Burlington, VT (US);

Kevin N. Ogg, Burlington, VT (US);

Richard J. Rassel, Colchester, VT (US);

Valarmathi C. Shanmugam, Essex Junction, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Stitched integrated circuit (IC) chip layout design structures are disclosed. In one embodiment, a design structure embodied in a machine readable medium used in a design process includes: an integrated circuit (IC) chip layout exceeding a size of a photolithography tool field, the IC chip layout including: a plurality of stitched regions including at least one redundant stitched region or at least one unique stitched region; and for each stitched region: a boundary identification identifying a boundary of the stitched region at which stitching occurs.


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