The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2010
Filed:
Nov. 17, 2006
Jeffrey P. Bradford, Rochester, MN (US);
Richard W. Doing, Raleigh, NC (US);
Richard J. Eickemeyer, Rochester, MN (US);
Wael R. El-essawy, Austin, TX (US);
Douglas R. Logan, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
William E. Speght, Austin, TX (US);
Lixin Zhang, Austin, TX (US);
Jeffrey P. Bradford, Rochester, MN (US);
Richard W. Doing, Raleigh, NC (US);
Richard J. Eickemeyer, Rochester, MN (US);
Wael R. El-Essawy, Austin, TX (US);
Douglas R. Logan, Austin, TX (US);
Balaram Sinharoy, Poughkeepsie, NY (US);
William E. Speght, Austin, TX (US);
Lixin Zhang, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A processor includes an execution unit and instruction sequencing logic that fetches instructions for execution. The instruction sequencing logic includes a branch target address cache having a branch target buffer containing a plurality of entries each associating at least a portion of a branch instruction address with a predicted branch target address. The branch target address cache accesses the branch target buffer using a branch instruction address to obtain a predicted branch target address for use as an instruction fetch address. The branch target address cache also includes a filter buffer that buffers one or more candidate branch target address predictions. The filter buffer associates a respective confidence indication indicative of predictive accuracy with each candidate branch target address prediction. The branch target address cache promotes candidate branch target address predictions from the filter buffer to the branch target buffer based upon their respective confidence indications.