Over-current sensing during narrow gate drive operation of class d output stages

Abstract

Two transistors of a class D output stage are driven by complementary, variable duty cycle signals PWM+ and PWM−. When the pulse width of the PWM+ signal becomes too narrow for reliable operation of prior art over-current protection circuits sensing the drain to source voltage of FETdriven by PWM+, a Narrow Pulse Detector generates a signal indicative of this narrow pulse condition. A Negative Current Sense circuit measures the drain to source voltage across FETduring the much longer conduction time of FETdriven by PWM−. Because of the energy stored in the series inductor coupled to the output of the class D stage, a negative current flows through this FETduring its conduction time. The resulting drain to source voltage of FETis measured and compared to a threshold. If the voltage indicative of current is over the threshold, and the Narrow Pulse Detector output indicates a narrow pulse condition, then an inhibit signal is generated which reduces current. A second Negative Current Sense circuit is utilized to similarly detect over-current conditions when the pulse width of PWM− becomes too narrow for reliable operation of prior art over-current protection circuits, thus protecting both FETs in the class D output stage from excessive current.