The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2010
Filed:
Apr. 03, 2008
Hao Yu, Fremont, CA (US);
Sing W. Chin, Alameda, CA (US);
Bill C. Wong, Milpitas, CA (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A duty cycle correction circuit () for receiving an input clock signal () and generating an output clock signal () having a predetermined duty cycle includes a clock trigger circuit () generating the output clock signal () having a first clock edge triggered from the input clock signal and a second clock edge triggered from a delayed clock signal (); a charge pump circuit () receiving the output clock signal and generating charging and discharging currents for a capacitor (C) where a control voltage develops on the capacitor indicative of the duty cycle error of the output clock signal; a self-track bias circuit () receiving the control voltage and generating first and second bias voltages () in response to the control voltage; and a delay-locked loop circuit () receiving the output clock signal and the first and second bias voltages and generating the delayed clock signal.