The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2010
Filed:
Sep. 25, 2006
Hidekiyo Ozawa, Kasugai, JP;
Morihito Hasegawa, Kasugai, JP;
Hidekiyo Ozawa, Kasugai, JP;
Morihito Hasegawa, Kasugai, JP;
Fujitsu Microelectronics Limited, Yokohama, JP;
Abstract
An object of the present invention is to provide a DC-DC converter control circuit capable of maintaining, even when any one of a plural number of DC-DC converters enters the abnormal state due to the occurrence of a failure, a voltage relationship between the output voltage of the faulty DC-DC converter and the output voltage of another DC-DC converter. An error amplifier ERAG has an inverting input, a first non-inverting input, and a second non-inverting input. A first divided voltage VVprovided from a first voltage divider circuit VDis fed into the inverting input; a reference voltage eG from ground is fed into the first non-inverting input; and a second divided voltage VVprovided from a second voltage divider circuit VDis fed into the second non-inverting input. The error amplifier ERAG amplifies the error between the lower of the two voltage inputs fed into the two non-inverting inputs (i.e. the lower of the reference voltage eG and the second divided voltage VV), and the first divided voltage VVfed into the inverting input. The output terminal of the error amplifier ERAG is connected to the input terminal of a PWM unit PG.