The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2010

Filed:

Jul. 05, 2007
Applicants:

Toru Koizumi, Yokohama, JP;

Shigetoshi Sugawa, Atsugi, JP;

Isamu Ueno, Hadano, JP;

Tesunobu Kochi, Hiratsuka, JP;

Katsuhito Sakurai, Machida, JP;

Hiroki Hiyama, Atsugi, JP;

Inventors:

Toru Koizumi, Yokohama, JP;

Shigetoshi Sugawa, Atsugi, JP;

Isamu Ueno, Hadano, JP;

Tesunobu Kochi, Hiratsuka, JP;

Katsuhito Sakurai, Machida, JP;

Hiroki Hiyama, Atsugi, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01);
U.S. Cl.
CPC ...
Abstract

A MOS-type solid-state image pickup device includes a photoelectric conversion unit having a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type forming a pn-junction with the first semiconductor region, a third semiconductor region of the first conductivity type disposed at a light incident side of the second semiconductor region, and a transfer MOS transistor having the second semiconductor region, a fourth semiconductor region of the second conductivity type, and a gate electrode disposed on an insulating film on the first semiconductor region between the photoelectric conversion unit and the fourth semiconductor region to transfer a charge carrier from the second semiconductor region to the fourth semiconductor region. The photoelectric conversion unit and the transfer MOS transistor are disposed on a substrate. A fifth semiconductor region of the second conductivity type is arranged continuously to the second semiconductor region under the gate electrode, and a sixth semiconductor region of the second conductivity type having an impurity concentration lower than that of the fourth semiconductor region is arranged at a side of the gate electrode in the fourth semiconductor region. A drain of the transfer MOS transistor includes the fourth and sixth semiconductor regions, and a bias is applied to the drain, and the fifth semiconductor region is depleted during reading out the charge carrier from the second semiconductor region.


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