The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 27, 2010

Filed:

Mar. 23, 2007
Applicants:

Kanae Nakagawa, Kawasaki, JP;

Masataka Mizukoshi, Kawasaki, JP;

Kazuo Teshirogi, Kawasaki, JP;

Inventors:

Kanae Nakagawa, Kawasaki, JP;

Masataka Mizukoshi, Kawasaki, JP;

Kazuo Teshirogi, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

A substrate support () having a flat supporting surface () is prepared, and a semiconductor substrate () is fixed to the substrate supporting surface () by attaching a wiring forming surface () to the supporting surface () by suction, for example, by vacuum suction. On this occasion, the wiring forming surface () is forcibly flattened by being attached to the supporting surface () by suction, and therefore the wiring forming surface () becomes a reference plane for planarization of a back surface (). In this state, planarization processing is performed by mechanically grinding the back surface () to grind away projecting portions () of the back surface (). Hence, variations in the thickness of the substrate (especially, semiconductor substrate) are made uniform, and high-speed planarization is realized easily and inexpensively without disadvantages such as dishing and without any limitation on a wiring design.


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