The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 27, 2010
Filed:
Dec. 30, 2005
Heong Jin Kim, Chilgok-gun, KR;
Heong Jin Kim, Chilgok-gun, KR;
Dongbu HiTek Co., Ltd., Seoul, KR;
Abstract
Disclosed is a method for forming a non-volatile memory device, comprising the steps of: successively depositing a gate oxide and a floating gate material on a semiconductor substrate; depositing and selectively etching a first dielectric on the floating gate material to form a first dielectric pattern; forming a first floating gate oxide on the floating gate material; selectively etching the floating gate material with using the first dielectric pattern as a mask to form a floating gate pattern; forming an insulating layer on the floating gate pattern; etching a portion of the semiconductor substrate between neighboring floating gate patterns to form a trench in the substrate; depositing a control gate oxide on surfaces of the trench; depositing a control gate material to fill the trench and to cover the substrate surface; depositing a second dielectric on the control gate material; selectively etching the second dielectric and the control gate material to form a control gate pattern and a second dielectric layer; selectively removing the control gate pattern to form a source line pattern which extends from the substrate surface exposed in the trench to top surface of the second dielectric layer on the control gate pattern; forming an insulating layer on surface of the source line pattern; and forming source region in portion of the substrate, which is exposed by the source line pattern.