Programmable random logic arrays using pn isolation

Abstract

Disclosed are a programmable, random logic device array, and a method of forming such a device. The device comprises a substrate, and a semiconductor layer above the substrate. That semiconductor layer, in turn, includes a first region of a first semiconductor type, an array of spaced apart second regions of a second semiconductor type, and a plurality of space-charge regions. Each of the space charge regions extends around a respective one of the second regions and separates that one of the second regions from the first region of the semiconductor layer. The programmable, random, logic device array further comprises first and second sets of contacts. The first set of contacts are in electrical contact with areas of said first region of the semiconductor layer, and the second set of contacts are in electrical contact with the second regions.