Digital clock filter circuit for a gapped clock of a non-isochronous data signal having a selected one of at least two nominal data rates

Abstract

A clock filter circuit (), which serves for filtering the clock of non-isochronous data signals having a selected one of at least two nominal data rates, has an auxiliary clock source () that generates an auxiliary clock signal () with a pulse repetition rate which is in the range between the at least two predetermined data rates, a delay line () connected to the auxiliary clock source () for creating a set of mutually delayed copies of the auxiliary clock signal and a multiplexer () that switches in a cyclic order between the delayed copies according to predetermined rules, which depend on the selected data rate to generate a filtered clock signal (). A control circuit determines whether the rate of the filtered clock () signal must be increased or decreased as compared to said data signal and controls the multiplexer () to delay or advance the cyclical switching accordingly.