Multi-mode i/o circuitry supporting low interference signaling schemes for high speed digital interfaces

Abstract

A multi-mode I/O circuit or cell () is provided for transmitting and receiving data between ICs, where each IC contains at least one of the I/O circuits. Each data link includes transmitter circuitry () and receiver circuitry (). The transmitter circuitry sends data to a receiver circuitry in another IC, and the receiver circuitry receives data from a transmitter circuitry in another IC. The I/O circuit is constructed with CMOS-based transistors (e.g., CMOS or BiCMOS) that are selectively interconnected together by a plurality of switches to operate as two single-ended, current or voltage mode links, or as a single differential current or voltage mode link. In the preferred embodiment the transmitter circuitry sends data to the receiver circuitry in another IC over a first pair of adjacently disposed conductors, and the receiver circuitry receives data from the transmitter circuitry in another IC over a second pair of adjacently disposed conductors. The transmitter circuitry and the receiver circuitry are selectively configured by the plurality of switches for operating in a double single-ended voltage mode link mode, a double single-ended current mode link mode, a mode defined by a single differential voltage mode link with a single-ended input drive, a mode defined by a single differential voltage mode link with a differential input drive, a mode defined by a single differential current mode link with a single-ended input drive mode, and a mode defined by a single differential current mode link with a differential input drive. A common I/O circuit may also be provided, and programmed into either the transmitter or the receiver circuit configuration.