The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Jan. 31, 2008
Abhijat Goyal, Chandler, AZ (US);
Chai Ean E. Gill, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Abhijat Goyal, Chandler, AZ (US);
Chai Ean E. Gill, Chandler, AZ (US);
James D. Whitfield, Gilbert, AZ (US);
Freescale Semiconductors, Inc., Austin, TX (US);
Abstract
An electrostatic discharge (ESD) protection device (), coupled across input-output (I/O) () and common () terminals of a core circuit () that it is intended to protect from ESD events, comprises, multiple serially coupled ESD clamp stages (), each stage () comprising an interior node () and first () and second terminal () nodes wherein the first terminal node () of the first clamp stage () is coupled to the common terminal () and the second terminal node () of the last clamp stages () is coupled to the I/O terminals (). A resistance-capacitance ladder () is provided in parallel with some of the clamp stages (), with a resistance (R, R, Retc.) coupled to each of the nodes (()) of one of the ESD clamp stages () by first terminals thereof and capacitors (C, C, etc.) are coupled between second terminals of the resistances (R, R, Retc.). The clamp stages () are desirably bi-directional and a diode (D) may bridge one or more of the clamp stages (e.g.,) to provide different clamp voltages for different polarity ESD events.