Data buffering with readout latency for single-event upset tolerant operation

Abstract

Apparatus and method for outputting data from an integrated circuit having programmable logic for Single-Event Upset tolerant operation is described. Configuration memory associated with the programmable logic is read. Bits of the configuration memory read are error checked. Buffers are cycled to select one to load and another one to unload responsive to completion of each error checking cycle of the bits. For a cycle of the error checking, a first data portion is loaded into one buffer of the buffers for the cycle, it is verified whether the bits are valid for the cycle, and a second data portion is unloaded from another buffer of the buffers responsive to the bits being valid for the cycle.