The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 20, 2010
Filed:
Nov. 07, 2007
Yakov Roizin, Migdal Haemek, IL;
Evgeny Pikhay, Migdal Haemek, IL;
Efraim Aloni, Migdal Haemek, IL;
Adi Birman, Migdal Haemek, IL;
Daniel Nehmad, Migdal Haemek, IL;
Yakov Roizin, Migdal Haemek, IL;
Evgeny Pikhay, Migdal Haemek, IL;
Efraim Aloni, Migdal Haemek, IL;
Adi Birman, Migdal Haemek, IL;
Daniel Nehmad, Migdal Haemek, IL;
Tower Semiconductor Ltd., Migdal Haemek, IL;
Abstract
An electrically erasable/programmable CMOS logic memory cell for RFID applications and other mobile applications includes a tunneling capacitor, a control capacitor, and a CMOS inverter that share a single floating gate. A two-phase program/erase operation performs an initial Fowler-Nordheim (F-N) injection phase using the capacitors, and then a Band-to-Band Tunneling (BBT) phase using the CMOS inverter. Both the F-N injection and BBT phases are performed using low currents and low voltages (i.e., 5V or less). The tunneling and control capacitors are fabricated in isolated P-wells (IPWs) including both N+ and a P+ regions to enable the use of both positive and negative programming voltages during the F-N and BBT programming/erasing operations.