The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2010

Filed:

May. 21, 2007
Applicants:

Se-myeong Jang, Anyang-si, KR;

Makoto Yoshida, Suwon-si, KR;

Jae-rok Kahng, Seoul, KR;

Chul Lee, Seoul, KR;

Keun-nam Kim, Suwon-si, KR;

Hyun-ju Sung, Seoul, KR;

Hui-jung Kim, Seoul, KR;

Kyoung-ho Jung, Suwon-si, KR;

Inventors:

Se-Myeong Jang, Anyang-si, KR;

Makoto Yoshida, Suwon-si, KR;

Jae-Rok Kahng, Seoul, KR;

Chul Lee, Seoul, KR;

Keun-Nam Kim, Suwon-si, KR;

Hyun-Ju Sung, Seoul, KR;

Hui-Jung Kim, Seoul, KR;

Kyoung-Ho Jung, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01);
U.S. Cl.
CPC ...
Abstract

For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.


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