The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 20, 2010

Filed:

Aug. 12, 2002
Applicants:

Michael J. Haji-sheikh, Dekalb, IL (US);

James R. Biard, Richardson, TX (US);

Simon Rabinovich, Plano, TX (US);

James K. Guenter, Garland, TX (US);

Bobby M. Hawkins, Wylie, TX (US);

Inventors:

Michael J. Haji-Sheikh, Dekalb, IL (US);

James R. Biard, Richardson, TX (US);

Simon Rabinovich, Plano, TX (US);

James K. Guenter, Garland, TX (US);

Bobby M. Hawkins, Wylie, TX (US);

Assignee:

Finisar Corporation, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/66 (2006.01); G01R 31/26 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods of conducting wafer level burn-in (WLBI) of semiconductor devices are presented wherein systems are provided having at least two electrodes (). Electrical bias () and/or thermal power () is applied on each side of a wafer () having back and front electrical contacts for semiconductor devices borne by the wafer. A pliable conductive layer () is described for supplying pins on the device side of a wafer with electrical contact and/or also for providing protection to the wafer from mechanical pressure being applied to its surfaces. Use of a cooling system () is also described for enabling the application of a uniform temperature to a wafer undergoing burn-in. Wafer level burn-in is performed by applying electrical and physical contact () using an upper contact plate to individual contacts for the semiconductor devices; applying electrical and physical contact using a lower contact plate () to a substrate surface of said semiconductor wafer; providing electrical power () to said semiconductor devices through said upper and lower second contact plates from a power source coupled to said upper and lower contacts plates; monitoring and controlling electrical power () to said semiconductor devices for a period in accordance with a specified burn-in criteria; removing electrical power at completion of said period (); and removing electrical and physical contact to said semiconductor wafer ().


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