The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2010

Filed:

Aug. 14, 2007
Applicants:

Mark R. Beckenbaugh, Rochester, MN (US);

Aj Kleinosowski, Austin, TX (US);

Eric J. Lukes, Stewartville, MN (US);

Byron D. Scott, Rochester, MN (US);

Inventors:

Mark R. Beckenbaugh, Rochester, MN (US);

AJ KleinOsowski, Austin, TX (US);

Eric J. Lukes, Stewartville, MN (US);

Byron D. Scott, Rochester, MN (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H03K 19/00 (2006.01); H03K 19/177 (2006.01); H01L 27/088 (2006.01);
U.S. Cl.
CPC ...
Abstract

A logic book for a programmable device such as an application-specific integrated circuit (ASIC) achieves improved radiation tolerance by providing transistors of the same doping type in different well regions that are physically isolated by intervening well regions with complementary doping. For example, n-type field effect transistors (NFETs) may be located in two outer rows of the book with separate Pwell regions, while p-type transistors are located in two inner rows of the book sharing a common Nwell region. Since the NFETs in separate wells are physically isolated from each other, a circuit structure which uses two NFETs in the two outer rows is much less likely to suffer multiple upsets from a single radiation strike. More complicated embodiments of the present invention include additional transistor rows in the stack with isolated Nwells and Pwells.


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