The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Mar. 31, 2007
On-chip decoupling capacitance and power/ground network wire co-optimization to reduce dynamic noise
Min Zhao, College Station, TX (US);
Rajendran Panda, Round Rock, TX (US);
Min Zhao, College Station, TX (US);
Rajendran Panda, Round Rock, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A semiconductor power network () decoupling capacitance (decap) budgeting problem is co-optimized with a wiring enhancement problem, wherein the solution is formulated to minimize the total decap to be added or wiring changes (addition of wires ()) to be made to the network (). Voltage constraints, available white space and other constraints determine the amount of decap to be added. Wire enhancements and/or added decap can be distributed throughout a violation region () of the semiconductor circuit () design to reduce dynamic supply voltage noise so that dynamic network voltages are at all times maintained greater than a user-specified threshold voltage level ().