The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Jul. 21, 2006
Felix Sun-tsyr Wu, San Jose, CA (US);
Edwin Simon Petrus, Piedmont, CA (US);
Lyndon Charles Lim, San Jose, CA (US);
Felix Sun-Tsyr Wu, San Jose, CA (US);
Edwin Simon Petrus, Piedmont, CA (US);
Lyndon Charles Lim, San Jose, CA (US);
Ciranova, Inc., Santa Clara, CA (US);
Abstract
Systems and methods of laying out integrated circuits are disclosed. During the layout stage of an integrated circuit device, a fixed, physical geometry is created of the parameterized cells (PCells) included in the integrated circuit schematic. The systems include a proxy engine configured to save to cache the geometries created during the layout stage such that the geometries need not be recomputed when the design is opened after a save to disk operation, during which geometries may otherwise be destroyed. The proxy engine may further be configured to delegate requests for the creation of geometries to other components of the integrated circuit design system. In addition, the proxy engine may be configured to perform customized evaluations of PCells, other than or in addition to caching and delegation.