The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2010

Filed:

Sep. 21, 2007
Applicants:

Chang-min Jeon, Yongin-si, KR;

Hee-seog Jeon, Suwon-si, KR;

Hyun-khe Yoo, Suwon-si, KR;

Sung-gon Choi, Osan-si, KR;

Bo-young Seo, Suwon-si, KR;

Ji-do Ryu, Suwon-si, KR;

Inventors:

Chang-Min Jeon, Yongin-si, KR;

Hee-Seog Jeon, Suwon-si, KR;

Hyun-Khe Yoo, Suwon-si, KR;

Sung-Gon Choi, Osan-si, KR;

Bo-Young Seo, Suwon-si, KR;

Ji-Do Ryu, Suwon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention is directed to a non-volatile memory device and a method of operating the same. The non-volatile memory device includes a first transistor connected to an nth bitline and a second transistor connected to an (n+1)th bitline. The first transistor and the second transistor are serially coupled between the nth bitline and the (n+1)th bitline. The non-volatile memory device may include a 2-transistor 1-bit unit cell where a drain region and a source region of a memory cell have the same or similar structure. Since a cell array of a non-volatile memory device according to the invention may include a 2-transistor 2-bit unit cell, storage capacity of the non-volatile memory device may be doubled.


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