The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 13, 2010
Filed:
Nov. 16, 2007
Corey Kenneth Barrows, Colchester, VT (US);
Douglas W. Kemerer, Essex Junction, VT (US);
Stephen Gerard Shuma, Underhill, VT (US);
Douglas Willard Stout, Milton, VT (US);
Oscar Conrad Strohacker, Leander, TX (US);
Mark Steven Styduhar, Hinesburg, VT (US);
Paul Steven Zuchowski, Jericho, VT (US);
Corey Kenneth Barrows, Colchester, VT (US);
Douglas W. Kemerer, Essex Junction, VT (US);
Stephen Gerard Shuma, Underhill, VT (US);
Douglas Willard Stout, Milton, VT (US);
Oscar Conrad Strohacker, Leander, TX (US);
Mark Steven Styduhar, Hinesburg, VT (US);
Paul Steven Zuchowski, Jericho, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A design structure. The design structure includes: a first set of FETs having a designed first Vt and a second set of FETs having a designed second Vt, the first Vt different from the second Vt; a first monitor circuit containing at least one FET of the first set of FETs and a second monitor circuit containing at least one FET of the second set of FETs; a compare circuit configured to generate a compare signal based on a performance measurement of the first monitor circuit and of the second monitor circuit; a control unit responsive to the compare signal and configured to generate a control signal regulator based on the compare signal; and an adjustable voltage regulator responsive to the control signal and configured to voltage bias wells of FETs of the second set of FETs, the value of the voltage bias applied based on the control signal.