The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 13, 2010

Filed:

Jul. 23, 2007
Applicant:

Eui-hoon Hwang, Suwon-si, KR;

Inventor:

Eui-Hoon Hwang, Suwon-si, KR;

Assignee:

Samsung Mobile Display Co., Ltd., San #24 Nongseo-Dong, Giheung-Gu, Yongin, Gyunggi-Do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8238 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of fabricating a Complementary Metal-Oxide Semiconductor (CMOS) Thin Film Transistor (TFT) using a reduced number of masks includes: forming a buffer layer on the entire surface of a substrate; forming polysilicon and photoresist layers on the entire surface of the substrate having the buffer layer; exposing and developing the photoresist layer to form a first photoresist pattern having a first thickness in a region where a semiconductor layer of a first TFT is to be formed, a second thickness in a region where a channel and a Lightly Doped Drain (LDD) region of a second TFT are to be formed, and a third thickness in a region where source and drain regions of the second TFT are to be formed; etching the polysilicon layer using the first photoresist pattern as a mask to pattern the semiconductor layers of the first and second TFTs; performing a first ashing process on the first photoresist pattern to form a second photoresist pattern where the region having the third thickness has been removed from the first photoresist pattern; implanting a first impurity into the source and drain regions of the second TFT using the second photoresist pattern as a mask; performing a second ashing process on the second photoresist pattern to form a third photoresist pattern where the region having the second thickness has been removed from the first photoresist pattern; and implanting a second impurity into the second TFT using the third photoresist pattern as a mask to perform channel doping on the second TFT.


Find Patent Forward Citations

Loading…