The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2010

Filed:

Feb. 20, 2008
Applicants:

Tetsuo Hironaka, Hiroshima, JP;

Hans Jürgen Mattausch, Higashihiroshima, JP;

Tetsushi Koide, Higashihiroshima, JP;

Tai Hirakawa, Hiroshima, JP;

Koh Johguchi, Hiroshima, JP;

Inventors:

Tetsuo Hironaka, Hiroshima, JP;

Hans Jürgen Mattausch, Higashihiroshima, JP;

Tetsushi Koide, Higashihiroshima, JP;

Tai Hirakawa, Hiroshima, JP;

Koh Johguchi, Hiroshima, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A multi-port instruction/data integrated cache which is provided between a parallel processor and a main memory and stores therein a part of instructions and data stored in the main memory has a plurality of banks, and a plurality of ports including an instruction port unit consisting of at least one instruction port used to access an instruction from the parallel processor and a data port unit consisting of at least one data port used to access data from the parallel processor. Further, a data width which can be specified to the bank from the instruction port is set larger than a data width which can be specified to the bank from the data port.


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