The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 06, 2010

Filed:

Nov. 03, 2006
Applicants:

Jin-aeon Lee, Suwon-si, KR;

Yong-ha Park, Suwon-si, KR;

Young-jin Chung, Seongnam-si, KR;

Yun-kyoung Kim, Yongin-si, KR;

Inventors:

Jin-Aeon Lee, Suwon-si, KR;

Yong-Ha Park, Suwon-si, KR;

Young-Jin Chung, Seongnam-si, KR;

Yun-Kyoung Kim, Yongin-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 3/00 (2006.01); G06F 1/04 (2006.01); G06F 1/06 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G06F 13/42 (2006.01); H03K 23/40 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Digital logic processing devices capable of reduced power consumption may be provided. A digital logic processing device may include one or more processing elements, an input FIFO for storing data, a processing unit, and a clock controller circuit. The processing unit may process data from the input FIFO and the clock controller circuit may control a clock signal supplied to the input FIFO and the processing unit. The clock controller circuit may monitor whether there is data to be transferred to the input FIFO and states of the input FIFO and the processing unit and may control the clock signal.


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