The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Oct. 10, 2007
Philip NG, Cupertino, CA (US);
Sai Kai Tsang, Union City, CA (US);
Kris LI, Cupertino, CA (US);
Liqi Wang, San Jose, CA (US);
Jinshu Son, Saratoga, CA (US);
Philip Ng, Cupertino, CA (US);
Sai Kai Tsang, Union City, CA (US);
Kris Li, Cupertino, CA (US);
Liqi Wang, San Jose, CA (US);
Jinshu Son, Saratoga, CA (US);
Atmel Corporation, San Jose, CA (US);
Abstract
A method for preventing snap-back in a circuit including at least one MOS transistor having a parasitic bipolar transistor associated with it includes coupling a circuit node including at least one source/drain node of the at least one MOS transistor to a bias-voltage circuit and enabling the bias-voltage circuit to supply a potential to the at least one source/drain node of the at least on MOS transistor, the potential having a magnitude selected to prevent the parasitic bipolar transistor from turning on.