The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 06, 2010
Filed:
Aug. 27, 2007
Se-young Yang, Seoul, KR;
Wang-ju Lee, Gyeonggi-do, KR;
Se-Young Yang, Seoul, KR;
Wang-Ju Lee, Gyeonggi-do, KR;
Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;
Abstract
Provided is a wafer level chip scale package that reduces the parasitic capacitance generated between ball pads and the solder balls, and enhances the joint reliability between the ball pads and the solder balls. The wafer level chip scale package provides a conductive pattern in each ball pad section, on which a solder ball is mounted, so as to have a spiral or mesh shape, provides a space defined by the conductive pattern such that a first dielectric layer under the conductive pattern is exposed, and provides the solder ball on a top surface of each ball pad section such that part of the solder ball is inserted into the space defined by the conductive pattern. When viewed from the top, the dielectric layer is exposed from each ball pad section by an area of about 50% or less.