The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2010
Filed:
May. 11, 2007
Teng Chow Ooi, Penang, MY;
Yanzhong Xu, Santa Clara, CA (US);
Jeffrey T. Watt, Palo Alto, CA (US);
Haiming Yu, San Jose, CA (US);
Teng Chow Ooi, Penang, MY;
Yanzhong Xu, Santa Clara, CA (US);
Jeffrey T. Watt, Palo Alto, CA (US);
Haiming Yu, San Jose, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
Systems and methods are provided for computing write margins for dual-port memory. A design for a dual-port memory array cell is generated using a circuit design tool. A user modifies the design of the dual-port memory array cell to incorporate two voltage sources. The voltage sources are used to represent differential noise on the memory cell. A write margin calculation tool uses a circuit simulation tool to perform transient simulations of write-during-read operations on the modified dual-port memory array cell. During the transient simulations, the voltage level on the voltages sources is systematically varied. The write margin for the dual-port memory is determined by analyzing the results of the transient simulations for each of the voltage levels used for the voltage sources.