The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2010
Filed:
Nov. 19, 2004
Wei Lee New, Singapore, SG;
Tien Ping Chua, Singapore, SG;
Wei Lee New, Singapore, SG;
Tien Ping Chua, Singapore, SG;
Panasonic Corporation, Osaka, JP;
Abstract
A method and apparatus to produce high-level synthesis Register Transfer Level designs utilises a trade-off between power dissipation and area usage in data path allocation. Power dissipation and area constraints and a priority between them are input. An algorithm automatically decides the number of registers that are to be used, according to the specified priority and constraints specified. Power management formulations can be used to gear the allocation process to trade lower power management costs for equivalent savings in register areas. Multi-criteria optimisation Integer Linear Programming is utilised with heuristically determined power and area weightings to suit different predefined requirements of the chip design. Bipartite weighted Assignment is used to determine the number of registers to be used at every stage, through cost formulations and the Hungarian Algorithm.