The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7689887 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 30, 2010

Filed:

Dec. 21, 2007
Applicants:

Kevin W. Gorman, Fairfax, VT (US);

Emory D. Keller, Jericho, VT (US);

Michael R. Ouellette, Westford, VT (US);

Inventors:

Kevin W. Gorman, Fairfax, VT (US);

Emory D. Keller, Jericho, VT (US);

Michael R. Ouellette, Westford, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01); G06F 13/24 (2006.01); G01R 31/28 (2006.01); G01R 31/00 (2006.01); G01R 31/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A Built-In-Self-Test (BIST) state machine providing BIST testing operations associated with a thermal sensor device(s) located in proximity to the circuit(s) to which BIST testing operations are applied, and a design structure including the BIST state machine embodied in a machine readable medium are provided. The thermal sensor device compares the current temperature value sensed to a predetermined temperature threshold and determines whether the predetermined threshold is exceeded. A BIST control element suspends the BIST testing operation in response to meeting or exceeding said predetermined temperature threshold, and initiates resumption of BIST testing operations when the current temperature value normalizes or is reduced. A BIST testing methodology implements steps for mitigating the exceeded temperature threshold condition in response to determining that the predetermined temperature threshold is met or exceeded. These steps include one of: ignoring the BIST results of the suspect circuit(s), or by causing the BIST state machine to enter a wait state and adjusting operating parameters of the suspect circuits while in the wait state.


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