The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Apr. 14, 2008
Applicant:

Naoki Yamada, Osaka, JP;

Inventor:

Naoki Yamada, Osaka, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to the present invention, an intra-macro match determining circuitinternally determines whether or not n test outputs from each macro all have the same level. The result of the determination is combined with some of the test outputs, and the resultant signal is output to a tester. Thus, the determination result for a match is combined with the test outputs instead of a particular value. Consequently, the same expected value can also be used for individual macro testing, and output bits are assigned to each of the macros. Therefore, in internally performing a comparison with the expected value, the tester can easily detect defective macros.


Find Patent Forward Citations

Yamada, Naoki. (2010). Semiconductor device in which a plurality of memory macros are mounted, and testing method thereof (U.S. Patent No. 7688658). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7688658

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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