Semiconductor memory device with debounced write control signal

Abstract

A semiconductor memory device having a memory cell array, an input buffer, an output buffer, and an input-output control circuit that receives a write control signal and controls the input and output buffers. The output buffer generates a commencement signal indicating commencement of output. A mask generating circuit generates a mask signal with delayed active-to-inactive transitions from the commencement signal. A masking circuit passes the write control signal to the input-output control circuit while the mask signal is inactive, and holds the write control signal in the write-disabling state while the mask signal is active. The mask signal prevents unintended writing of data in the memory cell array when the write control signal is contaminated by noise from the output buffer.