The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Dec. 06, 2005
Applicants:

Ji-ho Hur, Seoul, KR;

Se-hwan Kim, Seoul, KR;

Jin Jang, Seoul, KR;

Inventors:

Ji-Ho Hur, Seoul, KR;

Se-Hwan Kim, Seoul, KR;

Jin Jang, Seoul, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N 3/14 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is an active pixel sensor array, which can reduce the number of elements and the size of capacitors by enabling a reset switching transistor to include a function of an optical sensor and to reset a pixel voltage with a power supply voltage VDD after a gate selection signal is outputted, and to reset a pixel voltage with a power supply voltage VDD by a coupling function in case that a gate selection signal is outputted. The active pixel image sensor having a gate driving circuit and a column driving circuit includes a pixel composed of a voltage supply unit for supplying a signal voltage to the column driving circuit; a gate selection unit for turning on according to a n+1-th gate selection signal and outputting a voltage based on a difference between a pixel voltage and a threshold voltage of the voltage supply unit; a reset switching unit for turning on according to a n+1-th gate selection signal and resetting the pixel voltage with a power supply voltage VDD; and a storage unit and a coupling unit for coupling so as to initialize the pixel voltage to be lower than the power supply voltage VDD just after the n+1-th gate selection signal is outputted.


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