Delay apparatus, and delay locked loop circuit and semiconductor memory apparatus using the same

Abstract

A delay apparatus, and a delay locked loop circuit and a semiconductor memory apparatus using the same are provided. A delay locked loop circuit includes a register controlled delay part that delays a plurality of clocks input during an initial operation by delay amounts among initial delay amounts to be varied, which are set according to initial state setting signals, and increases or decreases the set delay amounts according to a phase detecting signal after the initial operation, a phase comparator that compares a phase of any one of the plurality of clocks and a phase of any one of the plurality of clocks delayed by the register controlled delay part and outputs the phase detecting signal, and an initial state setting unit that generates the initial state setting signals.