The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

May. 09, 2008
Applicants:

Philip Wise, High Wycombe, GB;

Philip Clarke, Leatherhead, GB;

Inventors:

Philip Wise, High Wycombe, GB;

Philip Clarke, Leatherhead, GB;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/00 (2006.01); H03L 7/00 (2006.01); H04L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Circuitry and methods are disclosed for capturing data from a double-data rate signal received from a source circuit, converting the double-data rate signal to single and/or half rate data signals, and re-synchronizing the data to the destination circuit's clock signal. In one embodiment, a first set of registers converts a double-data rate signal synchronized to a full-rate clock signal to two single-data rate signals. A second set of registers converts the single-data rate signals to four half-data rate signals. A third set of registers synchronizes the half-rate data signals to a half-rate clock signal. In another embodiment, methods and circuitry are provided for determining the position of a data valid window of the half-data rate intermediate signals relative to the rising and falling edges of the half-rate clock signal and using that determination to select half-data rate intermediate signals captured on either a rising or falling edge of the half-rate clock signal, depending on which will provide greater accuracy.


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