The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 30, 2010
Filed:
Oct. 03, 2005
Seung-bum Hong, Seongnam-si, KR;
Ju-hwan Jung, Seoul, KR;
Hyoung-soo Ko, Seoul, KR;
Hong-sik Park, Seoul, KR;
Dong-ki Min, Seoul, KR;
Eun-sik Kim, Seoul, KR;
Chul-min Park, Yongin-si, KR;
Sung-dong Kim, Seongnam-si, KR;
Kyoung-lock Baeck, Busan-si, KR;
Seung-bum Hong, Seongnam-si, KR;
Ju-hwan Jung, Seoul, KR;
Hyoung-soo Ko, Seoul, KR;
Hong-sik Park, Seoul, KR;
Dong-ki Min, Seoul, KR;
Eun-sik Kim, Seoul, KR;
Chul-min Park, Yongin-si, KR;
Sung-dong Kim, Seongnam-si, KR;
Kyoung-lock Baeck, Busan-si, KR;
Samsung Electronics Co., Ltd., Suwon-si, KR;
Abstract
Provided are a resistive memory device having a probe array and a method of manufacturing the same. The resistive memory device includes a memory part having a bottom electrode and a ferroelectric layer sequentially formed on a first substrate; a probe part having an array of resistive probes arranged on a second substrate, with the tips of the resistive probes facing the ferroelectric layer so as to write and read data on the ferroelectric layer; and a binding layer which grabs and fixes the resistive probes on or above the ferroelectric layer. The method of manufacturing the resistive memory device includes forming a bottom electrode and a ferroelectric layer sequentially on a first substrate; forming an array of resistive probes on a second substrate; and wafer level bonding the first substrate to the second substrate using a binding layer such that tips of the resistive probes face the ferroelectric layer.