The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Aug. 24, 2005
Applicants:

James Karp, Saratoga, CA (US);

Daniel Gitlin, Palo Alto, CA (US);

Shahin Toutounchi, Pleasanton, CA (US);

Michael G. Ahrens, Sunnyvale, CA (US);

Jongheon Jeong, Palo Alto, CA (US);

Inventors:

James Karp, Saratoga, CA (US);

Daniel Gitlin, Palo Alto, CA (US);

Shahin Toutounchi, Pleasanton, CA (US);

Michael G. Ahrens, Sunnyvale, CA (US);

Jongheon Jeong, Palo Alto, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 47/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.


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