The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 30, 2010

Filed:

Jun. 25, 2007
Applicants:

Robert K. Leidy, Burlington, VT (US);

Paul D. Sonntag, Colchester, VT (US);

Peter J. Sullivan, Fairfax, VT (US);

Inventors:

Robert K. Leidy, Burlington, VT (US);

Paul D. Sonntag, Colchester, VT (US);

Peter J. Sullivan, Fairfax, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G03F 9/00 (2006.01); G03C 5/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for manufacturing a stitched space in a semiconductor circuit implements a photolithographic process for printing one or more image fields on a wafer surface, each image field corresponding to a portion of a circuit or device and including a space that is to be stitched in adjacent image fields. The space to be stitched that is produced from an image field is overlapped onto the space to be stitched produced from the adjacent image field, however, the overlapped space from the adjacent image fields is intentionally misaligned. The stitched space is then subject to the double light exposure dose to print the stitched space, with the result that an overlay tolerance of the stitched space is improved.


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