The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7685541 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 23, 2010

Filed:

May. 01, 2008
Applicants:

Jeffrey D. Stroomer, Lafayette, CO (US);

Roger B. Milne, Boulder, CO (US);

Isaac W. Foraker, Longmont, CO (US);

Sean A. Kelly, Boulder, CO (US);

Inventors:

Jeffrey D. Stroomer, Lafayette, CO (US);

Roger B. Milne, Boulder, CO (US);

Isaac W. Foraker, Longmont, CO (US);

Sean A. Kelly, Boulder, CO (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

Translation of high-level design blocks into a design specification in a hardware description language (HDL). Each block in the high-level design is assigned to a group. A set of attributes is identical between the blocks in a group. For each group of blocks, a respective set of parameters having different values on subblocks of at least two blocks in the group is determined. An HDL specification is generated for each group. The HDL specification for a group has for each parameter in the set of parameters, a parameter input.


Find Patent Forward Citations

Stroomer, Jeffrey. (2010). Translation of high-level circuit design blocks into hardware description language (U.S. Patent No. 7685541). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7685541

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