System and method for implementing a digital phase-locked loop

Abstract

An apparatus for implementing a digital phase-locked loop includes a voltage-controlled oscillator that generates a primary clock signal in response to a VCO control voltage. Detection means generates counter control signals, including count up signals and count down signals, to indicate a current relationship between the primary clock signal and a reference signal. An up/down counter then either increments or decrements a counter value in response to corresponding counter control signals. The counter value is then converted by a digital-to-analog converter into the VCO control voltage for adjusting the frequency of the primary clock signal generated by the voltage-controlled oscillator. In alternate embodiments, the foregoing up/down counter may be utilized to adjust the frequency of the voltage-controlled oscillator in proportion to the counter value by utilizing appropriate techniques other than generating a VCO control voltage with a digital-to-analog converter.