The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 23, 2010

Filed:

Feb. 04, 2008
Applicants:

Chung H. Lam, Peekskill, NY (US);

Matthew J. Breitwisch, Yorktown Heights, NY (US);

Roger W. Cheek, Somers, NY (US);

Alejandro G. Schrott, New York, NY (US);

Matthew D. Moon, Jeffersonville, VT (US);

Inventors:

Chung H. Lam, Peekskill, NY (US);

Matthew J. Breitwisch, Yorktown Heights, NY (US);

Roger W. Cheek, Somers, NY (US);

Alejandro G. Schrott, New York, NY (US);

Matthew D. Moon, Jeffersonville, VT (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/20 (2006.01);
U.S. Cl.
CPC ...
Abstract

The present invention in one embodiment provides a method of forming a memory device that includes providing an interlevel dielectric layer including a conductive stud having a first width; forming an stack comprising a metal layer and a first insulating layer; forming a second insulating layer atop portions of the interlevel dielectric layer adjacent each sidewall of the stack; removing the first insulating layer to provide a cavity; forming a conformal insulating layer atop the second insulating layer and the cavity; applying an anisotropic etch step to the conformal insulating layer to produce a opening having a second width exposing an upper surface of the metal layer, wherein the first width is greater than the second width; and forming a memory material layer in the opening.


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