The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 23, 2010
Filed:
Apr. 22, 2004
Ted Johansson, Djursholm, SE;
Ted Johansson, Djursholm, SE;
Infineon Technologies AG, Neubiberg, DE;
Abstract
A method in the fabrication of an integrated circuit including a PMOS varactor and an npn transistor, comprises the steps of (i) simultaneously forming buried n-doped regions () for the PMOS varactor and the npn transistor in a p-doped substrate (); (ii) simultaneously forming n-doped wells () above the buried n-doped regions (); (iii) simultaneously forming field isolation areas () around the n-doped regions (); (iv) forming a PMOS gate region () and a p-doped base each in a respective one of the n-doped wells (); and (v) simultaneously forming n-doped contacts to the buried n-doped regions (); the contacts being separated from the n-doped wells (). Source and drain regions may be formed in the PMOS n-well (inversion mode) or the PMOS n-doped contact may be formed in the PMOS n-well instead of being separated from there (accumulation mode).