The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Sep. 21, 2007
Katsumi Homma, Kawasaki, JP;
Hidetoshi Matsuoka, Kawasaki, JP;
Izumi Nitta, Kawasaki, JP;
Toshiyuki Shibuya, Kawasaki, JP;
Katsumi Homma, Kawasaki, JP;
Hidetoshi Matsuoka, Kawasaki, JP;
Izumi Nitta, Kawasaki, JP;
Toshiyuki Shibuya, Kawasaki, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
Delay analysis performed on a circuit having multiple parallel partial circuits (paths) involves recursively integrating two paths of the circuit using an all-element delay distribution that indicates delay based on performance of all circuit elements in a path and a correlation delay distribution that indicates delay based on correlation between circuit elements in the path. An all-element delay distribution is calculated for the integrated path using the all-element delay distributions of the two paths to be integrated. The all-element delay distributions and the correlation delay distributions of two paths to be integrated are used to calculate a total delay distribution for the integrated path. The total delay distribution is used with the all-element delay distribution for the integrated path to calculate a correlation delay distribution for the integrated path. Through recursive calculation, a delay distribution of the circuit is estimated.