The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 16, 2010
Filed:
Dec. 21, 2006
John L. Melanson, Austin, TX (US);
Zhong You, Austin, TX (US);
Scott Allan Woodford, Austin, TX (US);
Steven Randall Green, Austin, TX (US);
John L. Melanson, Austin, TX (US);
Zhong You, Austin, TX (US);
Scott Allan Woodford, Austin, TX (US);
Steven Randall Green, Austin, TX (US);
Cirrus Logic, Inc., Austin, TX (US);
Abstract
A hybrid analog/digital phase-lock loop for low-jitter synchronization provides a mechanism for generating a low-jitter clock from a timing reference that has a high jitter level. A numerically-controlled analog oscillator provides a clock output and has an input for receiving a rational number. The rational number represents a ratio between the frequency of the clock output and the frequency of another stable clock provided to the circuit. A counter divides the frequency of either the clock output or the stable clock, providing feedback or feed-forward control of the analog oscillator, respectively. The circuit also includes a digital phase-frequency detector for detecting an on-going phase-frequency difference between an input timing reference and an output of the divider and a digital loop filter for filtering the output of the phase-frequency detector to provide the rational number that controls the frequency of the numerically-controlled analog oscillator.