The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2010

Filed:

Nov. 22, 2006
Applicants:

Satoshi Kamiya, Tokyo, JP;

Hirokazu Ozaki, Tokyo, JP;

Inventors:

Satoshi Kamiya, Tokyo, JP;

Hirokazu Ozaki, Tokyo, JP;

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/56 (2006.01);
U.S. Cl.
CPC ...
Abstract

A scheduler and method for scheduling packet forwarding operations is provided. Packet forwarding request information associated with a first set of input port/output port combinations is received. Packet forwarding request information associated with a second set of input port/output port combinations different from the first set of input port/output port combinations is received, where the first set of input port/output port combinations and the second set of input port/output port combinations are selected to not conflict with each other. Packet forwarding for both the first set of input port/output port combinations at a first future time slot and the second set of input port/output port combinations at a second future time slot are simultaneously scheduling at a first scheduler and a second scheduler, respectively, based on the received packet forwarding request information. Reservation information for the first set of input port/output port combinations and the second set of input port/output port combinations is transferred to adjacent schedulers based on a module pattern, where the adjacent schedulers are responsible for scheduling additional sets of input port/output port combinations for the first and second future time slots, respectively.


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