The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2010

Filed:

May. 29, 2008
Applicants:

Kazuki Yamauchi, Kanagawa, JP;

Junya Kawamata, Kanagawa, JP;

Tsutomu Nakai, Kanagawa, JP;

Kenji Arai, Kanagawa, JP;

Hirokazu Nagashima, Kanagawa, JP;

Kenichi Takehana, Kanagawa, JP;

Inventors:

Kazuki Yamauchi, Kanagawa, JP;

Junya Kawamata, Kanagawa, JP;

Tsutomu Nakai, Kanagawa, JP;

Kenji Arai, Kanagawa, JP;

Hirokazu Nagashima, Kanagawa, JP;

Kenichi Takehana, Kanagawa, JP;

Assignee:

Spansion LLC, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/34 (2006.01);
U.S. Cl.
CPC ...
Abstract

Structures, methods, and systems for enhanced erasing operation for non-volatile memory are disclosed. In one embodiment, a semiconductor device which comprises a memory cell array having a plurality of non-volatile memory cells, a negative voltage generating circuit for applying a negative voltage to a word line of the memory cell array during an erasing operation of the memory cell array, and a positive voltage generating circuit for applying a positive voltage to a well of the memory cell array when the negative voltage reaches a predetermined voltage.


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