The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 16, 2010

Filed:

Dec. 06, 2006
Applicants:

Yong Won Kim, Daejeon, KR;

Eun Soo Nam, Daejeon, KR;

Ho Young Kim, Daejeon, KR;

Sang Seok Lee, Daejeon, KR;

Dong Suk Jun, Daejeon, KR;

Hong Yeol Lee, Choongcheongbuk-do, KR;

Seon Eui Hong, Daejeon, KR;

Dong Young Kim, Daejeon, KR;

Jong Won Lim, Daejeon, KR;

Myoung Sook OH, Daejeon, KR;

Inventors:

Yong Won Kim, Daejeon, KR;

Eun Soo Nam, Daejeon, KR;

Ho Young Kim, Daejeon, KR;

Sang Seok Lee, Daejeon, KR;

Dong Suk Jun, Daejeon, KR;

Hong Yeol Lee, Choongcheongbuk-do, KR;

Seon Eui Hong, Daejeon, KR;

Dong Young Kim, Daejeon, KR;

Jong Won Lim, Daejeon, KR;

Myoung Sook Oh, Daejeon, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/24 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided are a hetero-junction bipolar transistor (HBT) that can increase data processing speed and a method of manufacturing the hetero-junction bipolar transistor. The HBT includes a semi-insulating compound substrate, a sub-collector layer formed on the semi-insulating compound substrate, a pair of collector electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the sub-collector layer, a collector layer and a base layer disposed between the collector electrodes, a pair of base electrodes disposed at a predetermined distance apart from each other on a predetermined portion of the base layer, an emitter layer stack disposed between the base electrodes, and an emitter electrode that is formed on the emitter layer stack, and includes a portion having a line width wider than the line width of the emitter layer stack, wherein both sidewalls of the emitter electrode are respectively aligned with inner walls of the pair of base electrodes, and sidewalls of the collector layer and the base layer are located between outer sidewalls of the pair of base electrodes of the pair of base electrodes.


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