The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 09, 2010
Filed:
Sep. 11, 2007
Reinaldo A. Bergamaschi, Tarrytown, NY (US);
Sean M. Carey, Hyde Park, NY (US);
Brian W. Curran, Saugerties, NY (US);
Prabhakar N. Kudva, New York, NY (US);
Matthew E. Mariani, York Haven, PA (US);
Mark D. Mayo, Wappingers Falls, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
Reinaldo A. Bergamaschi, Tarrytown, NY (US);
Sean M. Carey, Hyde Park, NY (US);
Brian W. Curran, Saugerties, NY (US);
Prabhakar N. Kudva, New York, NY (US);
Matthew E. Mariani, York Haven, PA (US);
Mark D. Mayo, Wappingers Falls, NY (US);
Ruchir Puri, Baldwin Place, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A system for logic block timing analysis may include a controller, and storage in communication with the controller. The storage may provide delay-versus-conesize values of a logic block. The system may further include a fitting module to provide a delay-cone based upon the delay-versus-conesize values of the logic block. The system may also include a conesize parser that uses the delay-cone to provide delay values through the logic block. The conesize parser may be used to validate the design of the logic block by comparing the delay-cone with a desired cycle time.