The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7676776 B1

PDF
Full Text
Expired
Date of Patent:
Mar. 09, 2010

Filed:

Jun. 25, 2007
Applicants:

Giorgos Stellos Tsapepas, Poughkeepsie, NY (US);

David A. Webber, Poughkeepsie, NY (US);

Michael Hemsley Wood, Poughkeepsie, NY (US);

Inventors:

Giorgos Stellos Tsapepas, Poughkeepsie, NY (US);

David A. Webber, Poughkeepsie, NY (US);

Michael Hemsley Wood, Poughkeepsie, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for determining gate array distribution includes steps or acts of: randomly placing a plurality of test boxes in a logic circuit layout; counting the number of fill cells in each of the plurality of test boxes; recording the count; grouping the plurality of test boxes into two groups: a first group with local clock buffers and a second group without local clock buffers; determining the fill cell percentage of each of the plurality of test boxes; and flagging the test boxes with a poor distribution of gate array cells.


Find Patent Forward Citations

Loading…