Digital lock detector for phase-locked loop

Abstract

A digital lock detector for a phase-locked loop. The PLL generates a feedback clock according to a reference clock. The digital lock detector includes a match detector and an arbiter. When a first clock transitions, the match detector checks that whether a second clock transitions in a predetermined time window or not. The match detector generates a match signal if the second clock transitions in the predetermined time window. The arbiter counts a number of the successive match signals and generates a lock signal to indicate a lock state when the number exceeds a first predetermined number.